1. Field of the Invention
The present invention relates to priority multiplexing schemes, and more particularly to a dynamic multiple-input priority multiplexer (MUX) that is faster than conventional dynamic MUXs and which does not require select signal generation logic to ensure exclusive assertion of select inputs.
2. Description of the Related Art
Integrated circuits (ICs), particularly those implementing synchronous pipeline architectures, use a relatively large number registers. Register logic holds the outputs of devices and/or circuits for some period of time so that these outputs can be received by other devices/circuits. In clocked systems, including pipeline microprocessors, registers are employed to latch and hold the outputs of a given pipeline stage so that input circuits in a subsequent stage can receive the outputs during the period when the given pipeline stage is generating new outputs.
In conventional designs, it has been common practice to follow complex logical evaluation circuits with registers that latch and hold the outputs of the evaluation circuits. The “speed” of a register is generally measured in terms of its data-to-output time, that is, the sum of its setup time requirement and its clock-to-output time. The overall operating speed of the system is limited by the delays associated with the logic evaluation circuits plus the speed of the register.
To gain speed, logic designers are presently designing priority multiplexer (MUX) circuits that combine as much of the logic evaluation functions as possible with their corresponding registers. The priority MUX circuits may further use a dynamic multiple-input MUXing stage to gain speed since dynamic circuits are very fast compared to conventional logic evaluation configurations. In the general case, one of M data signals is selected based on assertion of one of M−1 select signals. It is the responsibility of the select signal generation logic to ensure that the select signal assertion is exclusive since otherwise the state of the dynamic logic evaluant is dictated by the state of all selected inputs in a NOR-type configuration.
As alluded to above, select signal generation logic must be used to ensure exclusivity so that only one of the select signals is asserted at any given time. This adds delay to logic evaluation and slows overall system speed. Also, an area penalty is imposed on this type of logic.